Heteroepitaxial layers such as silicon germanium (“SiGe”) layers grown on single crystalline substrates such as silicon enjoy an increasing popularity for manifold applications in semiconductor technology. However, due to the difference in lattice between the substrate and the heteroepitaxially grown layer, misfit and associated threading dislocations are formed during growth of the heteroepitaxial layer.
One approach to producing defect-free heteroepitaxial layers is the growth of a graded buffer layer of SiGe on a silicon substrate where the germanium percentage of the SiGe layer is gradually increased starting from the substrate. The increase in germanium concentration can reach 100% germanium at the surface of the graded buffer layer. Grading up of a heteroepitaxial layer stack, however, results in a high degree of surface roughness and waviness of the resulting structures. In particular, the surface of such a structure is highly degraded by the so-called “cross-hatch” phenomenon caused by a stress release during growth of the heteroepitaxial SiGe layer.
Since a controlled surface nanotopography and low roughness are key issues in utilizing heteroepitaxial structures for integrated circuits, the rough and wavy surface of the heteroepitaxial SiGe layer must be planarized to remove surface nanotopography, and must be further polished by a chemical-mechanical polishing (“CMP”) step to perfect surface roughness by keeping surface nanotopography at the same level. It is very difficult to balance the effects of planarization and polishing since geometry and surface nanotopography properties of the structure will be degraded by polishing.
U.S. Pat. No. 6,039,803 shows a method for improvement in the surface roughness and reduction of the dislocation pile-up density of a heteroepitaxial layer by growing such a layer on a miscut silicon substrate. The miscut substrate has a crystallographic orientation off-cut to an orientation from about 1° to about 8° offset from the [001] direction. Such miscut substrates, however, are not commonly available and are therefore too costly to have practical uses in heteroepitaxial layer manufacturing. Thus, further improvements in these methods are necessary, and these are now provided by the present invention.